1. Field of the Invention
The invention pertains to methods for determining failure rate and selecting best burn-in time which can provide both error range and risk estimation by numerical approach.
2. Description of the Prior Art
As the complexity of integrated circuits and the difficulties of market contest increase, quality and reliability of produced integrated circuits have became more important than ever. Therefore, how to control the qualities of produced integrated circuits, how to estimate failing risk of integrated circuits while they are used by end-users, and how to balance production cost and quality promise are some important challenges for the quality department of integrated circuits manufacturers.
In general, the relation between failure rate of integrated circuits and time, both for testing and for application of end-users, is usually called a bathtub curve. As shown in FIG. 1, with the increase of time (period), the bathtub curve can be divided into infant mortality period, normal life period and wear out period. Whereby, infant mortality period usually corresponds to failure induced by defects of fabrication, and usually lasts about several weeks; normal life period usually corresponds to some random failures, and usually lasts about twenty years, thirty years or more; wear out period usually corresponds to failure induced by long-time waste, and is continuously increased while time goes by.
Because most integrated circuits will have been replaced with new designs and new technologies before the wear out period is reached, manufacturers usually only need to test all produced integrated circuits through the infant mortality period to select all integrated circuit failures induced by imperfect fabrication. Thus, all tested integrated circuits are suitable for selling, and the only risk is some random failures. Moreover, elimination of these random failures and prolongation of normal life-time only can be achieved by improvements of fabrication of integrated circuits, can not be achieved by operation of quality department.
However, owing to limitation of time, it is impossible for the quality department to test all produced integrated circuits through both the infant mortality period and the normal life period, even only through the infant mortality period. As usual, the quality department only performs a stress test or an accelerated test to test produced integrated circuits through a specific period under a testing environment which is more harmful and dangerous for tested integrated circuits, and then the relation between the failure rate and testing time is measured. The difference between the testing environment and a normal operating environment is used to estimate the relation between failure rate and real time, which is the experienced time under the normal environment.
Indisputably, how to properly and correctly transform the failure rate versus testing time relation into the failure rate versus real time relation is the key about whether failure rate versus time relation can be properly acquired by the stress test.
Moreover, almost all well-known arts use mathematical formula to estimate the failure rate relation by some tested datas. For example, the popular mathematical formula is the chi square distribution : xcex="khgr"2[2(r+1)B]/2t. Herein, xcex is the failure rate, "khgr" is the chi square function, r is failing number, B is confidence and t is time, and value of "khgr" is consulted from a pre-established table.
Significantly, because the failure rate versus time relation is acquired by referring to the formula in accordance with testing records, well-known arts have the following disadvantages: (1) the difference between the experimental value and the theoretical value can not be found by the used formula; (2) the best burn-in time only can be acquired by experience or formula, it can not be acquired by the relation between the best burn-in time and the corresponding risk; (3) the reliability of produced integrated circuits can not be assured by ensuring the estimated value which is almost the best value in accordance with the comparison between the experimental value and the theoretical value.
As a short summary, it is obviously that conventional arts can not efficiently determine the failure rate versus time relation and select the best burn-in time. Thus, it is necessary to develop a new method to analysis the testing records of the stress test and to effectively improve efficiency of quality department.
Objects of the present invention at least include providing a numerical method for providing both error range and risk estimation.
Objects of the present invention further comprise providing a method for controlling qualities of produced integrated circuits, estimating failing risk of users of produced integrated circuits, and balancing requirements of both production cost and quality promise.
On the whole, one method provided by the invention at least includes following basic steps: providing numerous integrated circuits; performing a life-time testing process, wherein a failure rate versus testing time relation is established by measuring the life-time of each integrated circuit under a testing environment, an acceleration factor function also is established under the testing environment, and the acceleration factor function is related to the relationship between a testing time of the testing environment and a real time of a normal operating environment; performing a simulating process that a testing time function to simulate the failure rate versus testing time relation; performing a transforming process by using the acceleration factor function to transform the testing time function into a real time function, wherein a knee point of the real time function corresponds to an operation time which is the best burn-in time; and performing an integrating process to integrate the real time function through a calculating region to acquire an accumulated failure rate versus real time function, wherein the calculating region is a region in which the real time is larger than the best burn-in time.
Besides, while more than one integrated circuits are failed before the knee point, the method further comprises deleting part of testing records and re-calculating the best burn-in time until only one integrated circuit is failed before the knee point.